1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and the manufacturing method thereof, and more particularly, to a liquid crystal display (LCD) device with a low resistance line structure and the manufacturing method thereof.
2. Description of Related Art
In consideration of the manufacturing cost of integrated circuits and the rate of unit operation, the manufacturing technology of integrated circuits has evolved to ULSI (ultra large scale integration) so as to make the metal interconnection in the back-end of line tend to be multilayered and miniaturized. However, the first issue caused by the miniaturization of metal interconnection is the reduction of signal transmission rate, resulting from the capacitance formed from the dielectric layers between metal lines.
The circuit signal transmission rate depends on the value of resistance (R)× capacitance (C), i.e., the smaller the value of R×C, the faster the transmission rate. The conventional methods resolving resistance capacitance time delay (RC Delay) use the metals with lower resistance coefficient as metal lines or taking the materials with lower dielectric coefficient as the dielectric materials between metal layers, so as to enhance the line signal transmission rate.
LCD devices, as compared to typical Cathode Ray Tube monitors, have the advantages of low power consumption, small volume and non-radiation. Because development of thin-film transistor LCD devices is following the large-sized and high-resolution requirements, RC delay is serious. In order to enhance a TFT driving signal transmission rate, a metal having a low resistance rate, such as copper, silver and gold, is used as the metal line or the gate line of a flat panel display substrate to resolve RC delay.
Some problems arising from the utilization of copper materials need to be resolved, including fast oxidation, moisture corrosion, poor adherence, and inter-diffusion. In general, the multilevel structure is used for resolving the above disadvantages, but the copper lines in the multilevel structure increase the difficulty in the subsequent etching process.
The metal lines of conventional panels are designed as Al/Ti or Ti/Al/Ti (TiN), but the problem of the conventional design is high sheet resistance. In addition, when the panel has broken lines or foreign matter blocking the circuit, repair lines are usually needed to overcome the defect. However, the signal pathway is two to three times longer than the original pathway. As shown in FIG. 1A, when the circuit A from SATB5 line has the broken line 500 in the panel, the repair line (circuit B) is taken as the current source. The pathway of the repair line longer than the original path causes RC delay time to increase and the signal is weakened to form the irreparable weak-line. Thereby, the repair does not have efficiency.
In addition, after dry etching Gate 100 profile in TFT structure formed by the conventional process, the angle between the gate profile and the substrate 00 should be 60°˜80°, as shown in FIG. 2A. In practice, Gate 100 is in non-normal form and the profile is 90°, as shown in FIG. 2B. When the insulated layer 200 is sputtered on the gate, the step coverage of the insulated layer on the gate is worse and a crack 201 is formed. Thereby, S-G leakage comes into existence and the yield is influenced. Therefore, the inlay type gate line can prevent the above defects.
Although it is known that the utilization of copper can improve the above difficulties in the design of the conventional panel, a further problem of mismatched resistance occurs. Thereby, the improvement in the material can avoid the above difficulties in designing a panel, and the efficiency of manufacturing panels can be enhanced.